RAM cells fabricated with MOS technology are known in which a cell includes a standard flip-flop arranged from a pair of cross-coupled driver transistors, a pair of load resistors, a power supply line, a ground line, a pair of transfer transistors coupled to the flip-flop and arranged in conjunction with a pair of data lines and a word line for accessing data in the flip-flop. Such a cell is shown in U.S. Pat. Nos. 4,471,374 and 4,486,944 by Kim Hardee.
It is known to provide memory cells in which the word line, the gates of the driver transistors, the gates of the transfer transistors which form the word line, the load resistors and the supply line are all defined and fabricated in the same polysilicon layer. This is the case in the above mentioned U.S. patent specifications. In this particular example the ground line is a buried (n+) diffusion layer.
It is further known to provide a static RAM cell in which the gates of the driver transistors, the gates of the transfer transistors which form the word line and the supply line are all formed in the same polysilicon layer. In such a cell the load resistors have been formed in a second level of polysilicon lying above the first level, and insulated from the first level by a non-conducting film. Connections between the two levels of polysilicon are provided in this case by removing the non-conducting film in the required areas.
A disadvantage of this cell is the inability of the metal film (which forms the data lines) to cover adequately the additional vertical steps introduced by the second level of polysilicon. A second disadvantage is the processing complications introduced by the requirement to interconnect the two polysilicon layers.
A disadvantage of all the above known cells is the use of polysilicon word lines. Typically the resistance of the polysilicon layer will be greater than 20 ohms per square. This means that there is a long propagation delay down the word line, which is a very significant fraction of the access (or cycle) time of the memory device. In order to reduce the memory access time (and therefore produce higher speed RAMs) it is necessary to significantly reduce the propagation delay down the length of the word line.
A cell has been proposed in which a second level of metal forms a low resistance word conductor which runs on top of and in parallel with the polysilicon word line. The second metal word conductor is interconnected with the polysilicon word line at intervals along the length of the word line. This reduces the propagation delay down the word line to a small fraction of what it would be without the word conductor. However, a disadvantage of this implementation is the very significant additional processing complexity of a double metal technology.
Another way to reduce the resistance of the word line in to use a silicide or polysilicon/silicide ("polycide") low resistivity gate material in place of the relatively high resistivity polysilicon layer.
It is known to provide 4 transistor 2 resistor static RAM cells in which the gates of the two driver transistors, the gates of the two transfer transistors (and therefore word line) and the ground line are all formed in the same polycide layer. The two load resistors and the supply line are formed in a second level of polysilicon in a similar manner to the implementation having 2 overlying polysilicon layers. The disadvantages are the metal film's inability to adequately cover the vertical steps in the polysilicon layer, and the processing complications as described earlier.